1. Field of the Invention
The present invention relates to a data processor, particularly to a hardware for aligning operand data which is read from a memory and aligning operand data to be written into the memory. Further, the invention relates also to a read control circuit and a write control circuit therefor.
2. Description of the Related Art
When a processor of a data processor executes memory access, in the case where location of data on a data bus which connects the processor and a memory does not match the format of data processed in the processor, it is required to match the location of data, namely to carry out data aligning processing.
FIG. 1 is a schematic diagram illustrative of an example of relationship between data arrangement in the memory and the data size to be accessed by the processor.
For example, assume that address space of the processor and data transferring size are both 32 bits as shown at the left side in FIG. 1, and that three kinds of data types are processed; a byte (one byte) size 501, a half-word (two bytes) size 502 and a word (four bytes) size 503.
Also, assume that the memory is allocated with addresses in the unit of byte as shown at the right side in FIG. 1, and is logically separated by boundaries (word boundary) in the unit of word size.
When specifying data in the memory, one word divided by the word boundaries is specified by higher 30 bits of an access address signal, and lower two bits of the access address signal and a code (byte control code) obtained by decoding the access size signal specify which byte in the specified word is valid.
In the case of read access, valid data is outputted onto the data bus at a byte position indicated by the byte control code, by giving a word address and the byte control code to the memory. In the case of write access, only the data at the byte position indicated by the byte control code is written From the data bus onto the memory.
In the processor, three kinds of data types, byte data, half-word data and word data having formats designated by reference numerals 501, 502 and 503, respectively, in FIG. 1 are processed. Data position to be accessed on the data bus is determined by the address and the access size as shown in FIG. 1, and is different from the data format processed in the processor. Therefore, at accessing to the memory, it is required to align the data which has been read from the memory before it is inputted to the processor.
For example, the highest byte of each word is specified when the lower two bits of the access address signal are "00", the second byte from the highest byte of each word is specified when the lower two bits are "01", the third byte from the highest byte of each word is specified when the lower two bits of the access address signal are "10", and the lowest byte (fourth byte from the highest byte) of each word is specified when the lower two bits of the access address signal are "11".
On the other hand, the access size signal specifies three sizes, a byte (one byte) size 601 to 604, a half-word (two bytes) size 611 to 614 and a word (four bytes) size 621 to 624.
Accordingly, when byte size is specified by the access size signal and the lower two bits of the access address signal are "00", for example, the one byte hatched in the one word designated by numeral 601 is accessed.
When half-word size is specified by the access size signal and the lower two bits of the access address signal are "10", for example, the two bytes hatched in the one word designated by numeral 613 are accessed.
When word size is specified by the access size signal and the lower two bits of the access address signal are "11", for example, the four bytes hatched in the two words designated by numeral 624 are accessed.
In the conventional data processor, data aligning is carried out in a circuit (aligning circuit) exclusively provided for aligning processing as described in, for example, the Japanese Patent Application Laid-Open No. 4-18634 (1992). FIG. 2 shows the constitution of the aligning circuit disclosed in the Japanese Patent Application Laid-Open No. 4-18634 (1992).
In FIG. 2, numeral 301 designates a first bus (32-bit width), 302 designates a second bus (32-bit width), 303 designates a first register (32-bit width), 304 designates an access size signal indicating either a byte size, a half-word size or a word size, 305 designates the lower two bits of an access address signal, 306 designates an alignment control circuit, 307 designates a shift circuit, 308 designates a second register (56-bit width), and 309 designates a data bus (32-bit width).
In addition, the data bus 309 is connected to a memory not shown in the drawing.
In read accessing, 32-bit data read from the memory is temporarily stored in the second register 308 via the data bus 309. The data temporarily stored in the second register 308 is aligned by shifting in the shift circuit 307, and is outputted to the first bus 301.
In write accessing, 32-bit, data from the second bus 302 is temporarily stored in the first register 303. The data temporarily stored in the first register 303 is aligned by shifting in the shift circuit 307, is outputted to the data bus 309, and is stored in the memory.
Shift width in the shift circuit 307 is generated by the alignment control circuit 306 based on the information obtained from the access size signal 304 and the lower two bits 305 of the access address signal.
In the aligning circuit provided in the conventional processor, as described above, access data is shifted in accordance with the address and an access size information thereby to match the data allocation in the memory and the data format in the processor, while such a constitution is necessary that is capable of shifting the 32-bit data by up to 24 bits in order to align the data in the unit of one byte in the above example of the prior art. Therefore, the second register 308 is made to have 56-bit width.
Although the conventional data processor has an exclusive circuit (aligning circuit) for data aligning processing, the aligning circuit requires a circuit for shifting 32-bit data by up to 24 bits when one word comprises four bytes, and there has been problems of increased hardware size of these circuits and that a large area is occupied by these circuits on a chip when the circuits are built in an integrated circuit.